供应LV240A具有三态输出的八路缓冲器/驱动器逻辑IC
| 价 格： | 面议 | |
| 型号/规格： | LV240A,SN74LV240ADGVR | |
| 品牌/商标： | TI |
说明
These octal buffers/drivers are designed for 2-V to 5.5-V VCC operation.
The 'LV240A devices are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters.
These devices are organized as two 4-bit buffers/line drivers with separate output-enable (OE\) inputs. When OE\ is low, the device passes data from the A inputs to the Y outputs. When OE\ is high, the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
特性
- 2-V to 5.5-V VCC Operation
- Max tpd of 6.5 ns at 5 V
- Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C - Typical VOHV (Output VOH Undershoot)
>2.3 V at VCC = 3.3 V, TA = 25°C - Support Mixed-Mode Voltage Operation on All Ports
- Latch-Up Performance Exceeds 250 mA Per JESD 17
- ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
参数
| SN74LV240A | |
| Voltage Nodes(V) | 5, 3.3, 2.5 |
| Vcc range(V) | 2.0 to 5.5 |
| Input Level | LVTTL |
| Output Level | LVTTL |
| No. of Outputs | 8 |
| Output Drive(mA) | -8/8 |
| tpd max(ns) | 9 |
| Static Current | 0.02 |
| Logic | Inv |
| Technology Family | LV-A |
dzsc/17/7796/17779677.jpg
dzsc/17/7796/17779677.jpg
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