Stratix IV GX EP4SGX230
28,000 logic elements (L)
17,133K total memory Kbits
1,28 18x18-bit multipliers blocks
2 PCI Exprs hard IP blocks
74 user I/Os
8 phase locked loops (PLLs)
Stratix IV GX EP4SGX530
531,200 logic elements (L)
27,376K total memory Kbits
1,024 18x18-bit multipliers blocks
4 PCI Exprs hard IP Blocks
74 user I/Os
8 phase locked loops (PLLs)
FPGA 配置
JTAG and Fast Pive Parallel (FPP) configuration
内建 U Blaster 电路
内存
64 Flash with a 16-bit data bus
2 ZBT SSRAM
I2C EEPROM
Two DDR2 SO-DIMM Sockets
400 MHz clock rate
Maximum theoretical bandwidth of over 102 Gbps
Up to 8-Gbyte capacity in total
SD Card Socket
支持 SPI 以及 SD 1-bit 两种 SD Card 读取模式
按钮，开关与 LED
4 个按钮
4 个滑动开关
8 个 LED
8 位 DIP 开关
2 个七段数码显示管
2 个的七段数码显示管
On-Board Clocks
3 Programmable PLLs configured via FPGA
o HSMA, HS transceiver clock source
o SATA reference clock
o FPGA LVDS clock input
50MHz/100MHz oscillator
SMA 接头
2 SMA connector for external transceiver clock input
4 SMA connector for LVDS clock input/output
2 SMA connectors for clock output
1 SMA connector for external clock input
4 个 SATA 接口
Support SATA 3.0 standard 6Gbps signaling rate
Two host and two device ports
4 个千兆以太网接口
Integrated 1.25 GHz SERD
PCI Exprs x8 Edge Connector
Support connection speed of Gen1 at 2.5Gbps/lane to Gen2 at 5.0Gbps/lane
Connection tablished with PC motherboard with x8 or x16 PCI Exprs slot
Two 172-pins High Speed Mezzanine Card (HSMC)
2 female-HSMC connectors
I/O voltage 2.5V
Total of 12 high-speed transceivers at 8.5 Gbps
Total of 38 LVDS pair at 1.6 Gbps
两组40个接脚扩充槽
72个 I / O引脚及4个电源和接地线，拉到40-pin 扩充槽
用于40-pin 扩充槽的排线可利用 IDE 硬碟的40-pin 排线
I/O voltage 3.0V
U主/从控制器
合通用串行总线规范2.0修订版标准
支持数据传输、全速传输与低速传输
Support both U host and device
3种U 接口 (one te mini-AB for host/device and two te A for host)
支持PIO与DMA模
电源
28,000 logic elements (L)
17,133K total memory Kbits
1,28 18x18-bit multipliers blocks
2 PCI Exprs hard IP blocks
74 user I/Os
8 phase locked loops (PLLs)
Stratix IV GX EP4SGX530
531,200 logic elements (L)
27,376K total memory Kbits
1,024 18x18-bit multipliers blocks
4 PCI Exprs hard IP Blocks
74 user I/Os
8 phase locked loops (PLLs)
FPGA 配置
JTAG and Fast Pive Parallel (FPP) configuration
内建 U Blaster 电路
内存
64 Flash with a 16-bit data bus
2 ZBT SSRAM
I2C EEPROM
Two DDR2 SO-DIMM Sockets
400 MHz clock rate
Maximum theoretical bandwidth of over 102 Gbps
Up to 8-Gbyte capacity in total
SD Card Socket
支持 SPI 以及 SD 1-bit 两种 SD Card 读取模式
按钮，开关与 LED
4 个按钮
4 个滑动开关
8 个 LED
8 位 DIP 开关
2 个七段数码显示管
2 个的七段数码显示管
On-Board Clocks
3 Programmable PLLs configured via FPGA
o HSMA, HS transceiver clock source
o SATA reference clock
o FPGA LVDS clock input
50MHz/100MHz oscillator
SMA 接头
2 SMA connector for external transceiver clock input
4 SMA connector for LVDS clock input/output
2 SMA connectors for clock output
1 SMA connector for external clock input
4 个 SATA 接口
Support SATA 3.0 standard 6Gbps signaling rate
Two host and two device ports
4 个千兆以太网接口
Integrated 1.25 GHz SERD
PCI Exprs x8 Edge Connector
Support connection speed of Gen1 at 2.5Gbps/lane to Gen2 at 5.0Gbps/lane
Connection tablished with PC motherboard with x8 or x16 PCI Exprs slot
Two 172-pins High Speed Mezzanine Card (HSMC)
2 female-HSMC connectors
I/O voltage 2.5V
Total of 12 high-speed transceivers at 8.5 Gbps
Total of 38 LVDS pair at 1.6 Gbps
两组40个接脚扩充槽
72个 I / O引脚及4个电源和接地线，拉到40-pin 扩充槽
用于40-pin 扩充槽的排线可利用 IDE 硬碟的40-pin 排线
I/O voltage 3.0V
U主/从控制器
合通用串行总线规范2.0修订版标准
支持数据传输、全速传输与低速传输
Support both U host and device
3种U 接口 (one te mini-AB for host/device and two te A for host)
支持PIO与DMA模
电源
